VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design

Avnesh VERMA; Sunil DHINGRA; M. K. SONI

Makale detayları

VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design

Yazarlar:

Avnesh VERMA | Sunil DHINGRA | M. K. SONI

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2009 Vol.17 Issue 3, pp.327-336

Belge Tipi:

Makale

Yayın Tarihi:

2/2009

Belge Dili:

Türkçe

Document ID (Org No.):

2000744011

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632

Özet:

 

The Field Programmable Gate Array (FPGA) is an on field  programmable device which can be designed for different applications.  Various types of software are available for its synthesis.  The cell  placement depends upon the designing and programming languages used  for FPGA. In this paper cell placement technique of FPGA architecture  is analyzed for the application of Space Vector Pulse Width Modulation  (SVPWM) technique used in speed control of an induction motor.  The  modulation pulses are produced due to the various components activated  and their interconnection in Configurable Logic Blocks (CLBs).  Few of  its components are so analyzed to find out the reason for their  desired output response.  This survey has also been conducted to find  the correlation of LUTs and formulation of output.

 

The Field Programmable Gate Array (FPGA) is an on field  programmable device which can be designed for different applications.  Various types of software are available for its synthesis.  The cell  placement depends upon the designing and programming languages used  for FPGA. In this paper cell placement technique of FPGA architecture  is analyzed for the application of Space Vector Pulse Width Modulation  (SVPWM) technique used in speed control of an induction motor.  The  modulation pulses are produced due to the various components activated  and their interconnection in Configurable Logic Blocks (CLBs).  Few of  its components are so analyzed to find out the reason for their  desired output response.  This survey has also been conducted to find  the correlation of LUTs and formulation of output.

Makale detayları

VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design

Yazarlar: Avnesh VERMA | Sunil DHINGRA | M. K. SONI

Yayıncı: TUBITAK

Dergi: Turkish Journal of Electrical Engineering and Computer Science 2009 Vol.17 Issue 3, pp.327-336

Belge Tipi: Makale

Yayın Tarihi: 2/2009

Belge Dili: Türkçe

Document ID (Org No.): 2000744011

Sıklık: İki Aylık

eISSN: 1303-6203

pISSN: 1300-0632

Sayı

Yazarlar:

Avnesh VERMA | Sunil DHINGRA | M. K. SONI

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2009 Vol.17 Issue 3, pp.327-336

Belge Tipi:

Makale

Yayın Tarihi:

2/2009

Belge Dili:

Türkçe

Document ID (Org No.):

2000744011

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632