Optimizing FPGA-based CNN accelerator for energy efficiency   with an extended Roofline model

SAYED OMID AYAT; Mohamed KHALIL-HANI; AB AL-HADI AB RAHMAN

Makale detayları

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Yazarlar:

SAYED OMID AYAT | Mohamed KHALIL-HANI | AB AL-HADI AB RAHMAN

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2018 Vol.26 Issue 2, pp.919-935

Belge Tipi:

Makale

Yayın Tarihi:

3/2018

Belge Dili:

Türkçe

Document ID (Org No.):

2000735292

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632

Özet:

 

In recent years, the convolutional neural network (CNN)   has found wide acceptance in solving practical computer vision and image   recognition problems. Also recently, due to its flexibility, faster   development time, and energy efficiency, the field-programmable gate array   (FPGA) has become an attractive solution to exploit the inherent parallelism   in the feedforward process of the CNN. However, to meet the demands for high   accuracy of today's practical recognition applications that typically have   massive datasets, the sizes of CNNs have to be larger and deeper.   Enlargement of the CNN aggravates the problem of off-chip memory bottleneck   in the FPGA platform since there is not enough space to save large datasets   on-chip. In this work, we propose a memory system architecture that best   matches the off-chip memory traffic with the optimum throughput of the   computation engine, while it operates at the maximum allowable frequency.   With the help of an extended version of the Roofline model proposed in this   work, we can estimate memory bandwidth utilization of the system at   different operating frequencies since the proposed model considers operating   frequency in addition to bandwidth utilization and throughput. In order to   find the optimal solution that has the best energy efficiency, we make a   trade-off between energy efficiency and computational throughput. This   solution saves 18% of energy utilization with the trade-off having less   than 2% reduction in throughput performance. We also propose to use a   race-to-halt strategy to further improve the energy efficiency of the   designed CNN accelerator. Experimental results show that our CNN accelerator   can achieve a peak performance of 52.11 GFLOPS and energy efficiency of   10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which   outperforms most previous approaches.

Makale detayları

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Yazarlar: SAYED OMID AYAT | Mohamed KHALIL-HANI | AB AL-HADI AB RAHMAN

Yayıncı: TUBITAK

Dergi: Turkish Journal of Electrical Engineering and Computer Science 2018 Vol.26 Issue 2, pp.919-935

Belge Tipi: Makale

Yayın Tarihi: 3/2018

Belge Dili: Türkçe

Document ID (Org No.): 2000735292

Sıklık: İki Aylık

eISSN: 1303-6203

pISSN: 1300-0632

Sayı

Yazarlar:

SAYED OMID AYAT | Mohamed KHALIL-HANI | AB AL-HADI AB RAHMAN

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2018 Vol.26 Issue 2, pp.919-935

Belge Tipi:

Makale

Yayın Tarihi:

3/2018

Belge Dili:

Türkçe

Document ID (Org No.):

2000735292

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632