Low leakage power gating technique for subnanometer CMOS circuits

KAVITHA MANICKAM; GOVINDARAJ THANGAVEL

Makale detayları

Low leakage power gating technique for subnanometer CMOS circuits

Yazarlar:

KAVITHA MANICKAM | GOVINDARAJ THANGAVEL

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2016 Vol.24 Issue 6, pp.5011-5024

Belge Tipi:

Makale

Yayın Tarihi:

11/2016

Belge Dili:

Türkçe

Document ID (Org No.):

2000741386

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632

Özet:

 

Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low-power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces  maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16{\%} energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under  variation of different operating parameters.

Makale detayları

Low leakage power gating technique for subnanometer CMOS circuits

Yazarlar: KAVITHA MANICKAM | GOVINDARAJ THANGAVEL

Yayıncı: TUBITAK

Dergi: Turkish Journal of Electrical Engineering and Computer Science 2016 Vol.24 Issue 6, pp.5011-5024

Belge Tipi: Makale

Yayın Tarihi: 11/2016

Belge Dili: Türkçe

Document ID (Org No.): 2000741386

Sıklık: İki Aylık

eISSN: 1303-6203

pISSN: 1300-0632

Sayı

Yazarlar:

KAVITHA MANICKAM | GOVINDARAJ THANGAVEL

Yayıncı:

TUBITAK

Dergi:

Turkish Journal of Electrical Engineering and Computer Science 2016 Vol.24 Issue 6, pp.5011-5024

Belge Tipi:

Makale

Yayın Tarihi:

11/2016

Belge Dili:

Türkçe

Document ID (Org No.):

2000741386

Sıklık:

İki Aylık

eISSN:

1303-6203

pISSN:

1300-0632